As integrated circuit devices have become able to perform more functions within a single integrated circuit chip, the manufacturers of integrated circuit chips have developed ways of automatically and quickly responding to orders for custom chips to perform specific functions for specific applications. On the one hand, gate array manufacturers apply custom metallization layers as a final step in a standard manufacturing process in order to connect transistors located within a semiconductor substrate to perform a particular logic function ordered by a customer. On the other hand, for customers who make frequent design changes, who want only small numbers of identical devices, or who may not have fully tested a new design, user programmable integrated circuit chips are available. In a user programmable device, there are many pass transistors which can be turned on or off to connect or not connect corresponding lines to logic circuits, to other lines, or output pins. By turning on the proper combination of pass transistors and connecting the proper set of lines a user can obtain a desired logic function. The user can reprogram a different design into the chip by turning on different combinations of pass transistors.
Xilinx, Inc. the assignee of the present invention, manufactures configurable logic arrays having a higher level of integration than typical programmable logic arrays. A Xilinx configurable logic array includes an array of logic blocks, each of which can be configured to perform a desired logic function (each logic block combining multiple AND, OR, MUX gates or FLIP-FLOPs for example). The Xilinx configurable logic array also includes interconnect lines which can be programmed to connect individual logic blocks to achieve the overall complex logic function provided by the entire chip. In the current Xilinx products, two kinds of configurable blocks are used in a configurable logic array chip. Around the perimeter of the chip, and connected to each of the external pins are input/output logic blocks which can be programmed to connect input buffers or output buffers to the pin and to perform some logic functions. In the interior of the chip are logic blocks which do not offer the input/output buffer option but offer more logic functions within a single block.
FIG. 1 shows part of one of the configurable logic array chips for which automatic programming is available. Configurable input/output blocks IO1 through IO15 are shown. Configurable logic blocks CLB11-CLB14, CLB21-CLB24, CLB31-CLB34 and CLB41-CLB44 are shown. Each of the configurable blocks implements a plurality of logic gates such as AND, OR, XOR, INVERT, and MUX, as well as TRISTATE buffers and FLIPFLOP's which can be combined to implement a plurality of more complex logic functions.
The logic gates of a logic block are formed into flexible functions which are specified when the block is configured. For example the logic block may include a four-input AND gate. Zero, one two, three or four AND gate inputs need be used, the unused inputs being connected to the positive voltage supply. An input signal may pass directly or through an inverter to the AND gate. Since gates within a block are physically located and connected together in the substrate and adjoining layers of the semiconductor material, any desired one of a plurality of functions such as AND, OR, NAND, NOR, XOR of two inputs A and B can be performed by electronic components located in close physical proximity, therefore the signal delay caused by the logic block is minimal in spite of the flexibility and complexity of the logic block. One type of logic block is programmed to provide a desired function of several input signals by loading memory cells of a look-up table with the truth table of a desired logic function. This way great flexibility is achieved with minimum signal delay.
These configurable blocks each have input and output leads for receiving input signals and providing output signals. These leads are shown in FIG. 1 as short lines extending outward from each of the blocks and not connected to other portions of the array. These configurable blocks also have configuration leads not shown in FIG. 1 for programming the particular logic function or loading the truth table. The configuration leads determine what logic function will be applied by the block to signals entered on its input leads to generate a signal placed by the block on its output lead or leads. These logic blocks are discussed in U.S. Pat. No. 4,706,216 issued Nov. 10, 1987, which is incorporated herein by reference.
Available to connect these logic blocks to each other are interconnect lines with programmable interconnects, such as shown in FIG. 2. FIG. 2 shows in more detail a smaller portion of a configurable logic array chip with the interconnects lines for connecting one configurable logic block (CLB) or input/output block (IOB) to another CLB or IOB. Some of the interconnect lines are short segments which extend only a short part of the distance across the entire array, and others typically extend in one dimension the entire length or width of the array. FIG. 2b is a legend showing meanings for the marks in FIG. 2a. Diagonal lines indicate programmable pass transistors for connecting horizontal lines to vertical lines. Each transistor will have one current carrying terminal connected to a horizontal line and one to a vertical line. The control terminals of the transistors are not shown in FIG. 2a but are each connected to a memory cell into which a zero or one is entered. The zero or one in the memory cell causes the horizontal line to be connected or not connected to the vertical line. Transistors are also placed at ends of segmented lines to control the continuity of adjacent segments. Each of these transistors is also controlled by a memory cell. FIG. 2c shows in more detail this full-exchange interconnection indicated by an "X" in FIG. 2a. Line 90-4 is segmented from line 90-1 in that it is connected to line 90-1 by N-channel pass transistor T5 when memory cell M5 holds a logical 1 and disconnected from line 90-1 when memory cell M5 holds a logical 0. Likewise line 90-4 is connected to line 90-3 by transistor T1 when memory cell M1 holds a logical 1 and disconnected when memory cell M1 holds a logical 0. A set of memory cells thus controls the configuration of the interconnect lines interconnecting the logic blocks in the array. FIGS. 2a through 2d are discussed more full in U.S. patent application Ser. No. 07/158,011, now U.S. Pat. No. 4,870,302, incorporated herein by reference.
FIG. 3a shows one possible CLB which is part of a configurable logic array and can be configured to perform many different logic functions. FIG. 3a shows combinatorial function generator 354 having input lines 381-385 for receiving logic block inputs a-3 and input lines 367 and 380 for receiving output signals from D-flipflops 352 and 357 respectively. Combinatorial function generator 354 also provides two combinatorial output functions F and G on lines 374 and 378, each of which may serve as input to either or both flipflops 352 and 357 as controlled by multiplexers 350, 351, 355 and 356. Output functions F and G may also be provided as logic block output signals X and Y respectively on lines 395 and 396 as controlled by multiplexers 353 and 358. Which functions are actually implemented by the logic block of FIG. 3a depends upon the settings of configuration control lines not shown in FIG. 3a. For an embodiment similar to that of FIG. 3a having four input lines A-D instead of the five input lines 381-385 of FIG. 3a, configuration control lines are shown in FIG. 3b as lines extending from RAM 108 or 109 to select multiplexer 110 or 111. Combinatorial function generator 354 of FIG. 3a generates two cominatorial functions F and G just as block 100 of FIG. 3b generates two combinatorial functions F1 and F2. FIG. 3b is discussed in U.S. Pat. No. 4,706,216, ibid. Combinatorial function generator 354 can generate any combinatorial function of five variables, or can generate two functions of four variables each. In current Xilinx logic blocks combinatorial function generator 354 is programmed by loading a truth table into a row of memory cells. As is well known, an n-input multiplexer can select one of 2.sup.n locations in response to an n-bit address. Function generator 354 is a multiplexer which reads one of 32 (2.sup.5) memory cells in response to an address which comprises the five input signals on lines 381-385, or alternatively reads one of sixteen memory cells to provide a first function of four of the variables on a first output line, and reads one of a second sixteen memory cells to provide a second function of any four of the five variables on a second output line 378. The operation of the logic block of FIG. 3a is described more thoroughly in the Xilinx "Programmable Gate Array Data Book", copyright 1988 by Xilinx, Inc., available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
A logic array including configurable blocks such as shown in FIG. 3a or 3b and interconnect lines such as shown in FIG. 2a can be configured to perform a multiplicity of complex logic functions. For example, it can be programmed to perform the function which is represented by the schematic diagram of FIG. 3c. The schematic of FIG. 3c includes input buffers, logic gates AND1OUT, XOR1OUT, OR1OUT, and OR2OUT, flip flops Q1OUT and Q2OUT, and output buffers. As shown in FIG. 3d, the input and output buffers are provided by input/output blocks P2 through P9. These blocks are located at the periphery of the logic array chip. Gates AND1OUT and OR1OUT and flip flop Q1OUT are implemented in logic block AB; gate XOR1OUT and flip flop Q2OUT are implemented in logic block AC, and gate OR2OUT is implemented in logic block AA. Logic blocks AA, AB, and AC can be of the type shown in FIG. 3b. By placing the output of buffers P9, P8, and P7 (FIG. 3d) on leads A, B, and C (FIG. 3b) respectively, setting MUX 104 of FIG. 3b (by loading a memory cell not shown) to provide signal A, MUX 105 to provide signal B, and MUX 106 to provide signal C, and by loading the appropriate truth table into 8-bit RAM 109, signals A, B, and C will cause multiplexer 111 to select the value from RAM 109 to represent the function in FIG. 3d of a two input AND gate plus a third signal serving as input to a two input OR gate. By setting MUX 114 to provide this output as signal F1 and setting MUX 126 to provide this signal as input to flip flop 121, flip flop 121 can be configured to implement flipflop Q1OUT of FIG. 3d. Multiplexers 122 and 142 of FIG. 3b can be configured to provide the Qff output signal of flip flop 121 as the Y output of the logic block. In this way the logic block of FIG. 3b implements the logic shown in block AB of FIG. 3d. similarly, other logic blocks of the type shown in FIG. 3b can implement the logic shown in blocks AC and AA of FIG. 3d.
Although memory cells have been used in existing logic arrays to control the logic functions performed by the arrays by writing values to the memory cells such as 8-bit RAM 109 of FIG. 3b during a configuration step, these memory cells have not been accessible to a user of the logic array for writing, storing, and reading data during operation of the logic array, as will now be explained.
The prior art memory cell of FIG. 4 comprises two inverters 41 and 42 connected in a loop such that the input of one inverter is connected to the output of the other inverter. Data line (or bit line) Dy is connected to or disconnected from the inverter by address line (or word line) Ax. Either output line Q or its inverse Q controls the state of one of the configuration transistors in a logic block such as shown in FIG. 3a or 3b. A preferred embodiment of this prior art memory cell achieves a known state on power-up and is described in U.S. Pat. No. 4,821,233 issued Apr. 11, 1989, incorporated herein by reference. The memory cell of FIG. 4 is loaded during configuration of the array. This configuration step requires that certain of the pins at the external perimeter of the array be used for configuration signals. When configuration is complete, these same external pins are most frequently configured to serve as data input or output pins. One or two pins have been used to switch the chip from configuration to operation mode but no provision has been available to alter these memory cells during operation after the configuration step is complete. Memory needed by a user during operation of such an array has generally been provided on a separate chip.
In some applications, it may be desirable to have memory distributed within the logic array, and to have the distributed memory available for access by the user during operation of the array. For example, in an application in which the user intends to use a configurable logic array chip as a combination central processing unit, a memory, and a first-in-first-out output buffer, it may be desirable to locate the memory storage close to where the information is generated. If the logic steps are performed by a logic block, storage of, say, one byte of information physically close to the logic block which generates the information requires less silicon area for interconnect lines and fewer interconnect transistors to route the generated information to its storage location.